Printed circuit boards in the for, of so-called “interposer substrates” have long been used as a primary medium for rerouting connection patterns of semiconductor devices, including in chip-scale packages (CSPs) for connection to higher-level packaging. The use of printed circuit boards is desirable since the processes for manufacturing them are well developed, inexpensive, and provide high yields. In addition, processes for packaging semiconductor devices with printed circuit boards have been refined over several decades of use. Further, printed circuit boards are themselves very reliable (i.e., they have low operational failure rates).
Due to the ever-increasing device densities and speeds of state-of-the-art semiconductor devices, the number of bond pads on semiconductor devices also continue to increase. The overall dimensions of state-of-the-art semiconductor devices do not typically increase, however. The dimensions of the circuit board interposer substrates that are used in packaging such devices, particularly in chip-scale packages, are likewise limited. Consequently, an ever-increasing number of conductive traces and terminals must be arranged within the relatively fixed area of a printed circuit board interposer substrate.
Until recently, increases in the numbers of conductive traces and terminals could be accommodated despite restrictions on the dimensions and areas of printed circuit board interposer substrates. As circuit design rules have approached the so-called “40/40” limit in which conductive traces have minimum widths of 40 μm and must be spaced at least 40 μm from each other and from other conductive structures, undesirable electrical issues, such as inductance between power and ground signals, have arisen. It is apparent that these problems would be magnified with even tighter design rules (i.e., conductive traces with widths of less than 40 μm that are closer than 40 μm to one another and to other conductive structures).
Accordingly, there are needs for interposer substrate design and manufacture processes, as well as for interposer substrates, that accommodate increased numbers of circuits without further tightened design rules.